Multiple mask step and scan aligner

ABSTRACT

A new optical lithographic exposure apparatus is described. The apparatus may comprise, for example, a lithographic stepper or scanner. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through one of the first mask and the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A step and scan method using the mask stage is provided. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus. The first mask and the second mask are aligned. The first mask is scanned. The wafer is then stepped. The second mask is scanned. By repeating this sequence across the wafer twice, the patterns of the first mask and the second mask are thereby superimposed in every field. The photoresist layer is developed to thereby create the patterning in the manufacture of the integrated circuit device.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to a method of fabricating semiconductorstructures, and more particularly, to an optical lithographic exposureapparatus with a multiple mask capability suitable for double-exposureprocesses in the manufacture of integrated circuits.

[0003] (2) Description of the Prior Art

[0004] As optical lithography is used to delineate 0.1 micron andsmaller features, the lithographic tools must work in a low k₁ region.The k₁, or Rayleigh's coefficient, for resolution, is given by theequation: $k_{1} = \frac{{CD} \times {NA}}{\lambda}$

[0005] where CD is the critical dimension of the line feature, NA is thenumerical aperture, and λ is the wavelength of the exposure light. Forexample, if the exposure wavelength is 193 nanometers and the NA is0.63, then k₁ is 0.39. At such a low k₁, extremely aggressive imageenhancing techniques have to be used to produce usable images for ICmanufacture. One such technique is the use of double exposures with twodifferent masks.

[0006] For example, an alternating phase shifting mask (PSM) may be usedwhen the desired feature size of an integrated circuit layer is on thesame order of magnitude as the wavelength of light used in thephotolithographic process. If a PSM is used, then a second exposure froma binary intensity mask (BIM) must be performed to remove any extralines caused by the phase shifting interference at the featureboundaries.

[0007] In a typical photolithographic mask, layer features, or traces,are formed on the mask in an opaque material such as chrome. This chromelayer is formed overlying a transparent quartz substrate. Light is shownthrough this mask to expose a photosensitive material, commonlyphotoresist, as defined by the mask pattern. After the photoresist isdeveloped, the photoresist will reflect a copy or a reverse copy of themask pattern.

[0008] However, in a phase shifting mask, an additional component isadded to the chrome and quartz system. Either through the application ofan additional transparent layer or the through the removal of a portionof the quartz layer to a specific depth, the optical properties arechanged in a part of the transparent (not covered by chrome) sections ofthe mask. Specifically, when light of the lithographic wavelength isshown through the mask, a phase shift is created between light wavesthat pass through the phase shifted area and the light waves that passthrough the non-phase shifted area. By shifting the phase of the lightby 180 degrees, nodes, or cancellations of energy will occur at opaqueboundaries between the phase shifted and non-phase shifted areas. Thisprinciple is used to create more sharply defined boundary conditionsduring the photolithographic exposure. Sharper definition leads toimproved pattern transfer.

[0009] In the case of the PSM method, two distinct reticles, the phaseshifting mask (BIM) and binary intensity mask (BIM) are used. Referringnow to FIG. 1, an alternating PSM mask 10 is shown for a simple feature.A chrome line 14 is formed on the mask. The chrome 14 is opaque andreflects exposure light away from the semiconductor wafer. Thetransparent regions of the mask 10 are divided into a zero degree, ornon-phase shifting, region 18 and a 180 degree, or phase shifting,region 22. The phase shifting region 22 is specially treated to causethe transmitted exposure light to be shifted 180 degrees with respect totransmitted exposure light traveling through the non-phase shiftingregion 18.

[0010] Referring now to FIG. 2, the BIM mask 30 is illustrated. Thepurpose of the BIM mask 30 is to remove any extra lines caused by theinterference of the phase shifted light and non-phase shifted light atthe boundaries of each region. The BIM mask 30 contains a chrome feature34 overlying the transparent substrate 38. The feature 34 is anappropriately oversized copy of the critical PSM feature of the PSMmask.

[0011] The PSM mask and the BIM mask are used sequentially. First, thesemiconductor wafer is coated with a photoresist layer. Second, the PSMmask of FIG. 1 is loaded into the mask stage of the optical lithographicstepper and aligned. The photoresist layer is then exposed, field byfield, to actinic light through the PSM mask. Third, the PSM mask isreplaced with the BIM mask of FIG. 2. The BIM mask must be aligned. Theundeveloped photoresist layer is exposed, field-by-field, to actiniclight through the BIM layer. At the end of the process, every field hasbeen exposed to thereby superimpose the patterns of the PSM mask and theBIM mask in every field.

[0012] Referring now to FIG. 3, a top view of the semiconductorsubstrate is shown. The photoresist layer 54 is developed. Thephotoresist layer 54 exhibits a very defined pattern overlying thesemiconductor substrate 50. The double-exposure method enables thecreation of smaller line widths than possible with a single, non-phaseshifted exposure.

[0013] If a conventional stepper is used for this process, the operatormust first install and then align the first mask. After exposing throughthe first mask, the operator must remove the first mask and install thesecond mask. This is because the conventional stepper can only hold andalign a single mask at a time. The second mask must be aligned prior tothe second exposure. It would be very advantageous and cost saving toeliminate a reticle change and alignment from the double-exposureprocess.

[0014] Several prior art approaches concern methods to double-expose anintegrated circuit and apparatus for holding masks. U.S. Pat. No.5,989,761 to Kawakubo et al teaches a method to expose photolithographicmasks onto a substrate. First and second masks, corresponding todifferent substrate layers, are used. The first and second masks areexposed with different apparatus having different exposure field sizes.The first mask is exposed on the first apparatus. A perpendicular errorand a mean value of rotation are detected for the first exposure. Thesecond mask is rotated based on the detected error of the first mask tocompensate and correct the error. U.S. Pat. No. 5,847,813 to Hirayanagidiscloses a mask holding apparatus for lithographic exposure masks. Theapparatus adds an inner frame to the conventional outer frame to therebyimprove support, thermal transfer, and electrical grounding. U.S. Pat.No. 4,924,258 to Tsutsui teaches a mask holding and conveying mechanism.The mask holding mechanism comprises a reference member, an aperture, aspring-biased first member, and a spring-biased second member.

SUMMARY OF THE INVENTION

[0015] A principal object of the present invention is to provide aneffective optical lithographic exposure apparatus and method of usethereof for patterning a photoresist layer in the manufacture of anintegrated circuit device.

[0016] A further object of the present invention is to provide anexposure apparatus capable of holding two masks in a fixed relativeposition for sequential exposure of the mask patterns onto asemiconductor wafer.

[0017] A yet further object of the present invention is to provide anexposure apparatus capable of aligning two masks prior to the sequentialexposure of the mask patterns onto a semiconductor wafer to thereby savetime.

[0018] Another yet further object of the present invention is to providean exposure apparatus capable of independently aligning two masks.

[0019] Another further object of the present invention is to provide aneffective and very manufacturable method to pattern a photoresist layerwherein the photoresist layer is sequentially exposed to actinic lightthrough two different masks.

[0020] Another yet further object of the present invention is to use atwo mask holding apparatus to sequentially expose the photoresist layerthrough a PSM mask and through a BIM mask to thereby enhance the imageof the pattern.

[0021] Another yet further object of the present invention is to exposesequentially the photoresist layer through the first mask and the secondmask without a mask change and alignment to thereby save time.

[0022] In accordance with the objects of this invention, a new opticallithographic exposure apparatus is described. The apparatus may comprisestep and scan capability. A wafer stage comprises a means of supportinga semiconductor wafer. A mask stage comprises a means of holding a firstmask and a second mask and maintaining a fixed relative position betweenthe first mask and the second mask. The mask stage may further comprisean independent means of aligning each mask. A light source comprises ameans to selectively shine actinic light through either the first maskor the second mask. An imaging lens is capable of focusing the actiniclight onto the semiconductor wafer. A means of stepping the mask stageacross the semiconductor wafer is provided.

[0023] Also in accordance with the objects of the present invention, anew method to pattern a photoresist layer in the manufacture of anintegrated circuit device is achieved. A photoresist layer is depositedoverlying a semiconductor substrate. A first mask and a second mask areloaded into a mask stage of an optical lithographic exposure apparatushaving a step and scan capability. The mask stage maintains a fixedrelative position between the first mask and the second mask. The firstmask and the second mask are aligned. The wafer is indexed to a startingfield that becomes the current field. The first mask is scanned toexpose the current field. The wafer is then indexed to a next fieldunexposed by the first mask. The stepping and scanning is repeated untilevery field on the semiconductor substrate is exposed with the firstmask. The wafer is then indexed to the starting field that becomes thecurrent field. The second mask is scanned to expose the current field.The wafer is then indexed to a next field unexposed by the second mask.The stepping and scanning is repeated until every field on thesemiconductor substrate is exposed with the second mask. The patterns ofthe first mask and the second mask are thereby superimposed in everyfield. The photoresist layer is developed to thereby complete thepatterning in the manufacture of the integrated circuit device.

[0024] Also in accordance with the objects of the present invention, anew method to pattern a photoresist layer in the manufacture of anintegrated circuit device is achieved. A photoresist layer is depositedoverlying a semiconductor substrate. A first mask and a second mask areloaded into a mask stage of an optical lithographic exposure apparatushaving a step and scan capability. The mask stage maintains a fixedrelative position between the first mask and the second mask. The firstmask and the second mask are aligned. The wafer is indexed to a startingfield that becomes the current field. The first mask is scanned toexpose the current field. The second mask is scanned to expose theadjacent field. The wafer is stepped to a next field unexposed by thefirst mask. The stepping and scanning is repeated until every field onthe semiconductor substrate is exposed. The wafer is indexed to thestarting field. The wafer is then stepped to a next field unexposed bythe second mask to become the current field. The second mask is scannedto expose the current field. The wafer is then indexed to the next fieldunexposed by the first mask to become the current field. The first maskis scanned to expose the current field. The stepping and scanning isrepeated until every field on the semiconductor substrate is exposed.The patterns of the first mask and the second mask are therebysuperimposed in every field. The photoresist layer is developed tothereby complete the patterning in the manufacture of the integratedcircuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the accompanying drawings forming a material part of thisdescription, there is shown:

[0026]FIG. 1 illustrates in simplified form an alternating phaseshifting mask (PSM).

[0027]FIG. 2 illustrates in simplified form a binary intensity mask(BIM).

[0028]FIG. 3 illustrates in simplified form a photoresist feature formedby double-exposure using the PSM mask of FIG. 1 and the BIM mask of FIG.2.

[0029]FIG. 4 illustrates in simplified form the key components of thepreferred embodiment of the optical stepper apparatus of the presentinvention.

[0030]FIGS. 5 and 6 illustrate two configurations of a mask stage forthe preferred embodiment apparatus of the present invention.

[0031]FIG. 7 illustrates the optional addition of a viewing microscopewith alignment marks to the apparatus of the present invention.

[0032]FIG. 8 illustrates, in flow chart form, a first preferredembodiment of the method of the present invention.

[0033]FIGS. 9 and 10 illustrate a semiconductor wafer processed by thefirst preferred embodiment of the method of the present invention.

[0034]FIG. 11 illustrates, in flow chart form, a second preferredembodiment of the method of the present invention.

[0035]FIGS. 12 through 14 illustrate a semiconductor wafer processed bythe second preferred embodiment of the method of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The embodiments disclose an optical lithographic exposureapparatus with a novel mask stage capable of holding and aligning twomasks at a time. This apparatus may comprise, for example, an opticalstepper or scanner. Further, it is preferred that the exposure apparatushave a step and scan capability. This apparatus is ideally suited fordouble-exposure processing in the manufacture of an integrated circuitdevice. In addition, two methods for double exposing using a two-maskstep and scan process are described. It should be clear to thoseexperienced in the art that the present invention can be applied andextended without deviating from the scope of the present invention.

[0037] Referring now particularly to FIG. 4, a simplified form of thepreferred embodiment of the apparatus of the present inventionillustrated. The key components of a new optical lithographic exposureapparatus are shown. This apparatus adds the ability to load and aligntwo masks and then expose a semiconductor wafer using each of thesereticles without a time consuming mask change and alignment step. Thesemiconductor wafer 274 is supported on a wafer stage 276.

[0038] An important aspect of the present invention is the novel maskstage 250. This mask stage 250 comprises a means of holding a first mask262 and a second mask 260. Each mask 260 and 262 is held in a separatefixture 256 and 258 in the mask stage 250. Each mask 260 and 262 can beindependently aligned to the wafer 274 and to the other mask. Oncealigned, the mask stage 250 maintains the fixed relative positionbetween the first mask 262 and the second mask 262.

[0039] The ability to independently hold and align the two masks 260 and262 allows an operator to load both masks at the beginning of thelithographic operation. Both masks 260 and 262 are then aligned. Eachmask can then be used for exposing fields on the semiconductor wafer 272without a time consuming mask change therebetween.

[0040] A light source 254 comprises a means of selectively shiningactinic light through either the first mask 262 or the second mask 260.The light source 254 may comprise, for example, a laser-based sourcewith a specific light wavelength. In the preferred embodiment, the lightsource 254 comprises a wavelength of 193 nanometers. The light source254 may include an optical circuit capable of flashing the actinic lightfor a specific length of time.

[0041] An imaging lens 270 is capable of focusing the actinic light thatpasses through either of the masks 260 and 262 onto the semiconductorwafer 274. The imaging lens 270 and the mask stage 250 are linked suchthat the image of the exposed mask will be focused onto a particularfield of the wafer 274 during each exposure step. Further, the imaginglens 270 and the mask stage 250 can be stepped, or indexed, from fieldto field across the semiconductor wafer.

[0042] The preferred application of the stepper apparatus having atwo-mask stage 250 is the double-exposure process described in FIGS. 1through 3. For example, an alternating PSM mask of the type shown inFIG. 1 may be loaded into the first mask fixture 258. A binary intensitymask (BIM) of the type shown in FIG. 2 may be loaded into the secondmask fixture 256. Both masks 260 and 262 are then aligned. The apparatusmay then be used to sequentially expose every field on the semiconductorwafer to actinic light through both the PSM mask 262 and the BIM mask260 such that the patterns of each mask are superimposed on each field.The novel ability to hold two masks, to maintain a fixed relationalposition between the two masks, and to align both masks prior toexposure provides a significant flexibility and time savings for theoperator.

[0043] Referring briefly now to FIG. 9, a semiconductor wafer 400 isillustrated. An array of fields 404 is shown. The exposure apparatus ofthe present invention exposes single fields 404 across the wafer. Whenfields are completed, the stepper indexes to the next field until theentire wafer is exposed. Each field may comprise several integratedcircuit die. The preferred embodiment exposure apparatus comprises astep and scan capability. Step and scan uses an illuminated slot whichis scanned over the mask to expose the wafer. While the lens remainsstationary, the mask and wafer move in a controlled fashion. The waferis stepped to a field and then the mask is scanned. In a 4X system, forexample, the mask moves 4 times faster than the wafer.

[0044] Returning now to FIG. 4, note that the scanning direction of theapparatus is shown. In this embodiment, the novel mask stage 250 isconfigured such that the first mask 262 and the second mask 260 areplaced side-by-side in the same direction as the scanning direction.Alternatively, the first mask and second mask may be configured acrossthe scanning direction.

[0045] Referring now to FIG. 5, one such configuration of the mask stageis shown in greater detail. Several important features of the presentinvention are shown. In this configuration, the mask stage 100 isconfigured such that the fixed relative position between the first mask104 and the second mask 108 is consistent with the scanning direction.Further, the first mask 104 and the second mask 108 are adjacent to eachother and in the same plane (coplanar).

[0046] Each wafer fixture 112 and 116 in the mask stage 100 has a set ofindependent alignment controls. The first fixture 112 may have an ‘x’lateral control 124 and a ‘y’ lateral control 120, or both. Similarly,the second fixture 116 may have an ‘x’ lateral control 132 and a ‘y’lateral control 128, or both. In addition, the first fixture 112 and thesecond fixture 116 may have angular controls 126 and 134 to adjust theangle of placement (θ) of each mask. The alignment controls are used tocarefully align the mask alignment marks 144 and 148 on the masks 104and 108 with the wafer alignment marks. These alignment controls maycomprise mechanical actuators or electromechanical actuators. Oncealigned, the mask stage 100 maintains alignment.

[0047] Referring now to FIG. 6, the mask stage 100 is shown in a secondscanning configuration. In this configuration, the mask stage 100 isconfigured such that the fixed relative position between the first mask104 and the second mask 108 is perpendicular with the scanningdirection. Again, the first mask 104 and the second mask 108 areadjacent to each other and in the same plane (coplanar).

[0048] Referring now to FIG. 7, an optional feature of the presentinvention is illustrated. A microscope viewer 216 provides acomplimentary alignment and viewing means for the operator. The operatoruses the microscope view 216 to register the alignment marks 208 and 212on the masks 200 and 204 with complimentary alignment marks on themicroscope objectives. This enables an off-axis alignment mechanism forthe operator.

[0049] The two-mask stage of the present invention may be extended to amultiple mask stage by adding an additional mask fixture and alignmentsystem. In this case, the first mask, second mask, and additional maskwould be held in a fixed relative position after alignment to facilitatea sequential exposure of a wafer using each mask.

[0050] Referring now to FIG. 8, a first preferred embodiment of a methodto pattern a photoresist layer in the manufacture of an integratedcircuit device is shown. This method uses the novel two-mask stage ofthe apparatus of the present invention to improve the double-exposurescenario outlined in FIGS. 1 through 3. First, a photoresist layer isdeposited overlying a semiconductor substrate in step 500. The firstmask and the second mask are loaded into the novel two-mask stage instep 504. Note that, in this first embodiment of the double-exposuremethod, either the consistent (FIG. 5) or the perpendicular (FIG. 6)mask configuration may be used. The first mask and the second mask arealigned in step 508.

[0051] The first mask scan is now performed. First, the wafer is indexedto the starting field to set the current field location in step 512.Referring to FIG. 9, the starting field 406 is the uppermost, left-sidefield of the wafer. Referring again to FIG. 8, the first mask is scannedto expose the current field in step 516. The wafer is then stepped tothe next field unexposed by the first mask to set a new current field instep 520. The scanning (step 516) and stepping (step 520) are repeateduntil all the fields on the wafer are exposed.

[0052] Referring once again to FIG. 9, a top view of the semiconductorwafer 400 is shown at the end of step 520. Every field 404 in the waferhas been exposed through the first mask at this point in the method.

[0053] Referring once again to FIG. 8, the second mask scan is nowperformed. The wafer is returned to the starting field 406 (in FIG. 9)to set the current field in step 524. The second mask is scanned toexpose the current field in step 528. The wafer is then stepped to thenext field unexposed by the second mask to set a new current field instep 532. The scanning (step 528) and stepping (step 532) are repeateduntil all the fields on the wafer are exposed.

[0054] Referring now to FIG. 10, the semiconductor wafer 400 is shown atthe end of step 532. Every field 404 has now been exposed through thesecond mask. Now, the pattern of the first mask and the second mask issuperimposed on every field 404 of the wafer 400.

[0055] Referring once again to FIG. 8, the photoresist layer isdeveloped to complete the method of patterning in step 536.

[0056] Referring now to FIG. 11, a second preferred embodiment of amethod to pattern a photoresist layer in the manufacture of anintegrated circuit device is shown. This method again uses the noveltwo-mask stage of the apparatus of the present invention to improve thedouble-exposure scenario outlined in FIGS. 1 through 3. First, aphotoresist layer is deposited overlying a semiconductor substrate instep 600. The first mask and the second mask are loaded into the noveltwo-mask stage in step 604. Note that, in this second embodiment of thedouble-exposure method, only the consistent (FIG. 5) mask configurationmay be used. The first mask and the second mask are aligned in step 608.

[0057] The wafer is indexed to the starting field to set the currentfield in step 612. Referring to FIG. 12, the starting field 306 is theuppermost, left-side field of the wafer. Referring again to FIG. 11, thefirst mask is scanned to expose the current field in step 616. Next, thesecond mask is scanned to expose the adjacent field in step 620. Notethat it is not necessary to step the mask stage to do this exposuresince the second mask is held adjacent to the first mask and is alreadypositioned to expose the field adjacent to the field exposed through thefirst mask. The wafer is now stepped to the next field unexposed by thefirst mask to set a new current field in step 624. The scanning (step616 and step 620) and stepping (step 624) are repeated until all thefields on the wafer are exposed.

[0058] Referring once again to FIG. 12, a top view of the semiconductorwafer 300 is shown at the end of step 624. Every field on the wafer hasbeen exposed through either the first mask 304 or the second mask 308during this first pass scan.

[0059] Referring once again to FIG. 11, the second pass scan is nowperformed. The wafer is returned to the starting field 306 (in FIG. 12)to set the current field in step 628. The wafer is stepped to the nextfield unexposed by the second mask to set a new current field. Referringnow to FIG. 13, the next field unexposed by the second mask 309 isshown. The second mask is scanned to expose the current field in step636. The wafer is then stepped to the next field unexposed by the firstmask to set a new current field in step 640. The first mask is nowscanned to exposed the current field in step 644. The scanning (step 636and step 644) and stepping (step 640) are repeated until all the fieldson the wafer are exposed.

[0060] Referring again to FIG. 13, the semiconductor wafer 300 is shownat the end of step 644. Now, the pattern of the first mask and thesecond mask is superimposed on every field 304 and 308 of the wafer 300.Note that only single mask scans are required at the beginning andending fields 312 of each row. These single mask exposure fields arecalled fill-in fields 312.

[0061] Referring now to FIG. 14, the fill-in fields may be completedusing a partial scan wherein the stepper is programmed to single exposethe beginning and ending fields 312 with the missing mask.

[0062] Referring once again to FIG. 11, the photoresist layer isdeveloped to complete the method of patterning in step 648.

[0063] The optical lithographic exposure apparatus described provides asignificant advantage over the prior art. The novel two-mask stageenables a double-exposure process without a time consuming mask changeand alignment. This facilitates the use of alternating phase shiftingmask (PSM) technology to produce very fine line width features in anintegrated circuit manufacturing process. The methods of patterning aphotoresist layer using the two-mask stage provide a very manufacturableapproach to phase shifting mask lithography.

[0064] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. An optical lithographic exposure apparatuscomprising: a wafer stage comprising a means of supporting asemiconductor wafer; a mask stage comprising a means of holding a firstmask and a second mask and maintaining a fixed relative position betweensaid first mask and said second mask; a light source comprising a meansof selectively shining actinic light through one of said first mask andsaid second mask; an imaging lens capable of focusing said actinic lightonto said semiconductor wafer; and a means of stepping said mask stageacross said semiconductor wafer.
 2. The apparatus according to claim 1wherein said apparatus consists of one of the group of: optical stepperand optical scanner.
 3. The apparatus according to claim 1 wherein saidfixed relative position between said first mask and said second maskcomprises adjacent, coplanar, and consistent with direction of saidstepping.
 4. The apparatus according to claim 1 wherein said fixedrelative position between said first mask and said second mask comprisesadjacent, coplanar, and perpendicular to direction of said stepping. 5.The apparatus according to claim 1 wherein said mask stage furthercomprises a means of aligning said first mask and said second maskwherein said aligning may be performed for both said first mask and saidsecond mask prior to any exposing and stepping.
 6. The apparatusaccording to claim 5 wherein said means of aligning comprises a singlelateral control (x) and an angular control (θ).
 7. The apparatusaccording to claim 5 wherein said means of aligning comprises twolateral controls (x and y) and an angular control (θ).
 8. The apparatusaccording to claim 5 wherein said means of aligning is independent foreach of said first mask and said second mask.
 9. The apparatus accordingto claim 1 wherein said mask stage further comprises a means of holdingat least one additional mask and maintaining a fixed relative positionbetween said first mask, said second mask, and said additional mask. 10.The apparatus according to claim 1 further comprising a microscopeviewer wherein alignment marks on said first mask and said microscopeviewer and said second mask and said microscope viewer may be aligned.11. An optical lithographic exposure apparatus comprising: a wafer stagecomprising a means of supporting a semiconductor wafer; a mask stagecomprising a means of holding a first mask and a second mask andmaintaining a fixed relative position between said first mask and saidsecond mask and a means of aligning said first mask and said second maskprior to exposing and stepping; a light source comprising a means ofselectively shining actinic light through one of said first mask andsaid second mask; an imaging lens capable of focusing said actinic lightonto said semiconductor wafer; and a means of stepping said mask stageacross said semiconductor wafer.
 12. The apparatus according to claim 11wherein said apparatus consists of one of the group of: optical stepperand optical scanner.
 13. The apparatus according to claim 11 whereinsaid fixed relative position between said first mask and said secondmask comprises adjacent, coplanar, and consistent with direction of saidstepping.
 14. The apparatus according to claim 11 wherein said fixedrelative position between said first mask and said second mask comprisesadjacent, coplanar, and perpendicular to direction of said stepping. 15.The apparatus according to claim 11 wherein said means of aligningcomprises a single lateral control (x) and an angular control (θ). 16.The apparatus according to claim 11 wherein said means of aligningcomprises two lateral controls (x and y) and an angular control (θ). 17.The apparatus according to claim 11 wherein said means of aligning isindependent for each of said first mask and said second mask.
 18. Theapparatus according to claim 11 wherein said mask stage furthercomprises a means of holding at least one additional mask andmaintaining a fixed relative position between said first mask, saidsecond mask, and said additional mask and a means of aligning saidadditional mask.
 19. The apparatus according to claim 11 furthercomprising a microscope viewer wherein alignment marks on said firstmask and said microscope viewer and said second mask and said microscopeviewer may be aligned.
 20. A method to pattern a photoresist layer inthe manufacture of an integrated circuit device comprising: depositing aphotoresist layer overlying a wafer; loading a first mask and a secondmask in a mask stage of an exposure apparatus wherein said mask stagemaintains a fixed relative position between said first mask and saidsecond mask; aligning said first mask and said second mask; indexingsaid wafer to a starting field to set a current field; thereafterscanning said first mask to expose said current field; thereafterstepping said wafer to a next field unexposed by said first mask to seta new said current field; thereafter repeating said scanning andstepping until every said field on said semiconductor substrate isexposed with said first mask; thereafter returning said wafer to saidstarting field to set said current field; thereafter scanning saidsecond mask to expose said current field; thereafter stepping said waferto a next field unexposed by said second mask to set a new said currentfield; thereafter repeating said scanning and stepping until every saidfield on said semiconductor substrate is exposed with said second maskto thereby superimpose the patterns of said first mask and said secondmask in every said field; and developing said photoresist layer tothereby complete said patterning in the manufacture of said integratedcircuit device.
 21. The method according to claim 20 wherein said fixedrelative position between said first mask and said second mask comprisesadjacent, coplanar, and consistent with direction of said steppingthrough.
 22. The method according to claim 20 wherein said fixedrelative position between said first mask and said second mask comprisesadjacent, coplanar, and perpendicular to direction of said steppingthrough.
 23. The method according to claim 20 wherein first maskcomprises a phase-shifting mask and wherein said second mask comprises abinary intensity mask.
 24. A method to pattern a photoresist layer inthe manufacture of an integrated circuit device comprising: depositing aphotoresist layer overlying a wafer; loading a first mask and a secondmask in a mask stage of an optical lithographic, stepper wherein saidmask stage maintains a fixed relative position between said first maskand said second mask; aligning said first mask and said second mask;indexing said wafer to a starting field to set a current field;thereafter scanning said first mask to expose said current field;thereafter scanning said second mask to expose an adjacent field;thereafter stepping said wafer to a next field unexposed by said firstmask to set a new said current field; and thereafter repeating saidscanning and stepping until every said field on said semiconductorsubstrate is exposed; thereafter returning said wafer to said startingfield to set said current field; thereafter stepping said wafer to anext field unexposed by said second mask to set a new said currentfield; thereafter scanning said second mask; thereafter stepping saidwafer to a next field unexposed by said first mask to set a new saidcurrent field; thereafter scanning said first mask to expose saidcurrent field; thereafter repeating said scanning and stepping untilevery said field on said semiconductor substrate is exposed to therebysuperimpose the patterns of said first mask and said second mask inevery said field; and developing said photoresist layer to therebycomplete said patterning in the manufacture of said integrated circuitdevice.
 25. The method according to claim 24 wherein said fixed relativeposition between said first mask and said second mask comprisesadjacent, coplanar, and consistent with direction of said steppingthrough.
 26. The method according to claim 24 wherein first maskcomprises a phase-shifting mask and wherein said second mask comprises abinary intensity mask.
 27. The method according to claim 24 wherein anyof said fields at the beginning and the end of rows of said fields isonly exposed through a single said mask.